1. Field of the Invention
The present invention relates to a semiconductor device for which high driving performance is required.
2. Description of the Related Art
Year by year full use of fine processing technology has enabled manufacturing of small semiconductor devices without lowering capability. This trend can also apply to a semiconductor element having high driving performance. The reduction of an ON resistance of the element per unit area has been achieved with the best use of fine processing technology. However, it is also a fact that lowering of withstanding voltage, which is caused by miniaturization of elements, hinders further improvement of the driving performance. Elements with various structures have been proposed in order to eliminate the trade-off between miniaturization and withstanding voltage. A trench gate MOS transistor is an example in a power MOS FET with a high withstanding voltage and high driving performance, which constitutes present mainstream. The trench gate MOS transistor has the highest packing density in integration among DMOS transistors having high withstanding voltage and high driving performance. The trench gate MOS transistor has, however, a longitudinal MOS structure in which current flows in a depth direction of a substrate. The transistor has extremely excellent performance as an element itself, but has a disadvantage when mounted on a chip with other IC elements. When mounting on a chip with other ICs is taken into consideration, a conventional lateral MOS structure can never be skipped.
A lateral trench gate transistor has been proposed as a method capable of reducing ON resistance per unit area without lowering withstanding voltage. In this transistor, a gate portion has a structure having a convex portion and a concave portion to gain a larger gate width (for example, refer to JP 3405681 B). FIGS. 4A to 4D are conceptual diagrams for the conventional art. Here, FIG. 4A is a plan view, FIG. 4B is a sectional view taken along the line 4B-4B′ in FIG. 4A, FIG. 4C is a sectional view taken along the line 4C-4C′ in FIG. 4A, and FIG. 4D is a sectional view taken along the line 4D-4D′ in FIG. 4A. Here, for convenience in viewing FIG. 4A, a gate electrode 003 and a gate insulating film 004 outside trenches are shown transparently. A bold line indicates an edge of the gate electrode 003. This art discloses the extension of a gate width per unit area of a lateral MOS transistor and the resultant reduction in ON resistance thereof with the gate portion 003 having a trench structure.
The above-mentioned art has, however, two problems.
(1) The first problem will be explained. FIG. 5 is a bird's-eye view obtained by taking out only a source region 001 or a drain region 002 shown in FIGS. 4A to 4D. Here, the gate oxide film 004 and the gate electrode 003 are not shown. In FIG. 5, the surface of the source region 001 or the drain region 002, which is dark-colored, and which contacts with a trench wall, is a portion 020 that contacts with a channel portion. The portion 020 that contacts with the channel portion exists on each of all the surfaces of the source region 001 or drain region 002, which contact with the trench wall. That is, in the structures of FIGS. 4A to 4D, dimensions of lengths d1, w1, and l2 determine a contact area between the source region 001 or drain region 002 and the channel portion. When the contact area is small, this area becomes a bottleneck as shown by a current flow 019 shown in FIG. 4D (a current density becomes dense in the source region and the drain region), which inhibits the reduction of the ON resistance. In order to increase the contact area it is sufficient to make the dimensions of lengths of the d1, w1, and l2 larger.
First, the length d1 is considered. The length d1, which corresponds to the depth of each of the source region 001 and the drain region 002 in the case where each of the source region 001 and the drain region 002 is formed through normal ion implantation, is generally shallow, several thousands Å, and there is a limit to its depth.
When the width of the convex portion of the trench is kept constant, a longer length for w1, which corresponds to the width of the concave portion of the trench, causes decrease in the number of trenches per unit area and decrease in the vertical contact area, resulting in decrease in the gate width. Enlargement of the length w1 is thus impossible.
As regards a method of lengthening the l2 as an overlap length between the source region 001 or the drain region 002 and the trench, it is clear that in the case where l2 is lengthened without changing the gate length, the area increases accordingly. Further, when it is supposed that the source region 001 and the drain region 002 are formed in self-alignment manner with the gate electrode 003, in order to lengthen l2, a method of shortening l1 or a method of increasing the length over which impurities of the source region 001 and the drain region 002 are diffused is considered; since there is limitation in shortening l1, the method of lengthening l2 through the diffusion of the impurities should be taken. However, this method also has limitation on the length, and additionally has a risk such as the reduction in concentration of the source region 001 or the drain region 002 caused by the excessive impurity diffusion. Actual implementation of the method is, therefore, difficult. That is, it is difficult to increase the contact area in the conventional art without changing the element area to reduce the ON resistance of the MOS transistor.
(2) The second problem is that there is a limitation to the trench depth. Increasing the trench depth can further increase the gate width per unit area. However, this only applies to the case in a well region 005. There is a limitation to the depth of the well region 005 formed by a general method. Thus, the trench cannot be deeper than the well region 005. If the trench is made deeper than the well region 005, a current leaks to the substrate.